The SIMM-Sys bus

Connector

The SIMM-Sys bus connector is a loosely defined layout for a 72-pin SIMM connector. About one half of the pins have fixed function and serves as a general-purpose asynchron I/O bus, power supply pins and PnP support pins. The other half of the pins can be used-defined meaning. There is however a set of default configurations for commonly used functions. If such a function (for example an RS-232 port) is available on a specific card it is highly recommended to use the pre-defined layout for those.

SIMM-Sys bus pin-out

Pin No.	Dir	Name	Description
1	O	RD	Active low read select signal.
2	O	UWE	Active low write select signal. Upper byte.
3	O	LWE	Active low write select signal. Lower byte.
4	I	RESET	Active low reset signal.
5	O	SEL0	Active low peripherial select signal.
6	O	SEL1	Active low peripherial select signal.
7	O	SEL2	Active low peripherial select signal.
8	I	IRQ0	Active low interrupt signal. Can be edge or level sensitive.
9	I	IRQ1	Active low interrupt signal. Can be edge or level sensitive.
10	I	IRQ2	Active low interrupt signal. Can be edge or level sensitive.
11	O	A0	Address lines
12	O	A1
13	O	A2
14	O	A3
15	O	A4
16	O	A5
17	O	A6
18	O	A7
19	O	A8
20	O	A9
21	I/O	D0	Data lines
22	I/O	D1
23	I/O	D2
24	I/O	D3
25	I/O	D4
26	I/O	D5
27	I/O	D6
28	I/O	D7
29	I/O	D8
30	I/O	D9
31	I/O	D10
32	I/O	D11
33	I/O	D12
34	I/O	D13
35	I/O	D14
36	I/O	D15
key
37	PWR	WAIT	Active low signal to introduce wait-states in the access cycles. Must be driven. with an open-collector driver. The pull-up resistor is provided on the CPU cards. Some CPU cards may not support this feature.
38	PWR	GND	Ground
39	PWR	GND	Ground
40	PWR	VCC_3	3.3V nominal power supply.
41	PWR	VCC_3	3.3V nominal power supply.
42	PWR	VCC_2_5	2.5V nominal power for core supply.
43	PWR	VCC_1_8	1.8V nominal power for core supply.
44	I	PROG	Active low programming signal.
45	I/O	IOC0	I/O group C
46	I/O	IOC1
47	I/O	IOC2
48	I/O	IOC3
49	I/O	IOC4
50	I/O	IOC5
51	I/O	IOC6
52	I/O	IOC7
53	I/O	IOC8
54	I/O	IOC9
55	I/O	IOC10
56	I/O	IOC11
57	I/O	IOB0	I/O group B
58	I/O	IOB1
59	I/O	IOB2
60	I/O	IOB3
61	I/O	IOB4
62	I/O	IOB5
63	I/O	IOA0	I/O group A
64	I/O	IOA1
65	I/O	IOA2
66	I/O	IOA3
67	I/O	IOA4
68	I/O	IOA5
69	I/O	IOA6
70	I/O	IOA7
71	O	PNPC	PnP I2C bus clock
72	I/O	PNPD	PnP I2C bus data

Notes:

Directions are seen from the CPU cards
SELx and IRQx signals are rotated for each extension card
Appropriate reset signal must be generated by the motherboard
Programming signal switches the CPU card into a special programming mode. Actual programming algorithm depends on the CPU card. This pin has a pullup resistor inside the CPU card.
PnP serial EEPROM must exists an all extension cards an motherboards. It will never exists on a CPU card. The motherboard also has to implement a switching functionality between PnP EEPROMs.

Alternate pinouts for I/O group C

Alternate pinout for synchronous serial I/O

Pin No.	Dir	Name	Description
45	I/O	RCLK0	Read bit-clock for serial port 0
46	I/O	RFS0	Read frame sync for serial port 0
47	I	RD0	Read data for serial port 0
48	I/O	TCLK0	Transmit bit-clock for serial port 0
49	I/O	TFS0	Transmit frame sync for serial port 0
50	O	TD0	Optional Transmit data for serial port 1
51	I/O	RCLK1	Optional Read bit-clock for serial port 1
52	I/O	RFS1	Optional Read frame sync for serial port 1
53	I	RD1	Optional Read data for serial port 1
54	I/O	TCLK1	Optional Transmit bit-clock for serial port 1
55	I/O	TFS1	Optional Transmit frame sync for serial port 1
56	O	TD1	Optional Transmit data for serial port 1

Alternate pinout for RS-232

Pin No.	Dir	Name	Description
45	O	DTR0	RS-232 port 0
46	O	RTS0
47	I	RXD0
48	I	DSR0
49	I	CTS0
50	O	TXD0
51	O	DTR1	Optional RS-232 port 1
52	O	RTS1
53	I	RXD1
54	I	DSR1
55	I	CTS1
56	O	TXD1

Alternate pinout for Ethernet

Pin No.	Dir	Name	Description
45			Ethernet port 0
46	I	RX-
47	I	RX+
48
49	O	TX-
50	O	TX+
51			Optional Ethernet port 1
52	I	RX-
53	I	RX+
54
55	O	TX-
56	O	TX+

Alternate pinout for USB

Pin No.	Dir	Name	Description
45			USB port 0
46	I/O	D+
47	I/O	D-
48
49
50
51			Optional USB port 1
52	I/O	D+
53	I/O	D-
54
55
56

Alternate pinout for IEEE-1394a

Pin No.	Dir	Name	Description
45			IEEE-1394a port 0
46	I/O	TPA+
47	I/O	TPA-
48
49	I/O	TPB+
50	I/O	TPB-
51			Optional IEEE-1394a port 1
52	I/O	TPA+
53	I/O	TPA-
54
55	I/O	TPB+
56	I/O	TPB-

Alternate pinout for CAN-Bus

Pin No.	Dir	Name	Description
45			CAN-Bus port 0
46	I	Rx0
47	I	Rx1
48
49	O	Tx0
50	O	Tx1
51			Optional CAN-Bus port 1
52	I	Rx0
53	I	Rx1
54
55	O	Tx0
56	O	Tx1

Alternate pinouts for I/O group B

Alternate pinout for timers

Pin No.	Dir	Name	Description
57	I	TC0	Timer 0 clock input
58	I	TG0	Timer 0 gate input
59	O	TO0	Timer 0 clock output
60	I	TC1	Timer 1 clock input
61	I	TG1	Timer 1 gate input
62	O	TO1	Timer 1 clock output