Preliminary
The scMaverick is a high performance, high capacity member of the SIMM-Sys CPU card line. It is built around the Cirrus Logic EP7312 chip. This chip contains an ARM7TDMI core running at 74MHz max., 8kBytes of cache, 48kBytes of SRAM and tons of on-chip peripherials. The chip also contains a built in SDRAM controller, features 32-bit external address and data buses and provides extreme low power consumption.
The card completes this set of excellent features with up to 8MBytes of 16-bit FLASH memory and up-to 64MBytes of 32-bit SDRAM memory. These features makes this device ideal as a central controller of a complex automation system, running off-the-self operation systems such as Linux or WindowsCE.
For more budget-minded customers there is a scaled-down version of the controller. The only difference between the full-blown and the lc (Low-Cost) version is the amount of SDRAM and FLASH memory it contains.
| scMaverick | scMaverick-lc | ||
|---|---|---|---|
| Clock speed | 74 | 74 | MHz |
| CPU speed | 74/49/18 | 74/49/18 | MHz |
| SRAM memory | 48 | 48 | kByte |
| SDRAM memory | 64 | 8 | MByte |
| FLASH memory | 8192 | 512 | kByte |
| Power supply | 3.3/2.5 | 3.3/2.5 | V |
| Pin No. | Dir | Name | Description |
|---|---|---|---|
| 1 | O | RD | Active low read select signal. |
| 2 | O | UWE | Active low write select signal. Upper byte. |
| 3 | O | LWE | Active low write select signal. Lower byte. |
| 4 | I | RESET | Active low reset signal. |
| 5 | O | SEL0 | Active low peripherial select signal. |
| 6 | O | SEL1 | Active low peripherial select signal. |
| 7 | O | SEL2 | Active low peripherial select signal. |
| 8 | I | IRQ0 | Active low interrupt signal. Can be edge or level sensitive. |
| 9 | I | IRQ1 | Active low interrupt signal. Can be edge or level sensitive. |
| 10 | I | IRQ2 | Active low interrupt signal. Can be edge or level sensitive. |
| 11 | O | A0 | Address lines |
| 12 | O | A1 | |
| 13 | O | A2 | |
| 14 | O | A3 | |
| 15 | O | A4 | |
| 16 | O | A5 | |
| 17 | O | A6 | |
| 18 | O | A7 | |
| 19 | O | A8 | |
| 20 | O | A9 | |
| 21 | I/O | D0 | Data lines |
| 22 | I/O | D1 | |
| 23 | I/O | D2 | |
| 24 | I/O | D3 | |
| 25 | I/O | D4 | |
| 26 | I/O | D5 | |
| 27 | I/O | D6 | |
| 28 | I/O | D7 | |
| 29 | I/O | D8 | |
| 30 | I/O | D9 | |
| 31 | I/O | D10 | |
| 32 | I/O | D11 | |
| 33 | I/O | D12 | |
| 34 | I/O | D13 | |
| 35 | I/O | D14 | |
| 36 | I/O | D15 | |
| key | |||
| 37 | PWR | WAIT | Active low signal to introduce wait-states in the access cycles. Must be driven. with an open-collector driver. The pull-up resistor is provided on the CPU card. |
| 38 | PWR | GND | Ground |
| 39 | PWR | GND | Ground |
| 40 | PWR | VCC_3 | 3.3V nominal power supply. |
| 41 | PWR | VCC_3 | 3.3V nominal power supply. |
| 42 | PWR | VCC_2_5 | 2.5V nominal power for core supply. |
| 43 | PWR | VCC_1_8 | 1.8V nominal power for core supply. (not used on this card) |
| 44 | I | PROG | Active low programming signal. |
| 45 | I/O | TxD | RS-232 port |
| 46 | I/O | RxD | |
| 47 | I | DSR | |
| 48 | I/O | DCD | |
| 49 | I/O | CTS | |
| 50 | O | DT0A | |
| 51 | I/O | SSICLK | Read bit-clock for serial port 1 |
| 52 | I/O | SSIRxF | Read frame sync for serial port 1 |
| 53 | I | SSIRxD | Read data for serial port 1 |
| 54 | I/O | SSICLK | Transmit bit-clock for serial port 1 |
| 55 | I/O | SSITxF | Transmit frame sync for serial port 1 |
| 56 | O | SSITxD | Transmit data for serial port 1 |
| 57 | I/O | PB0 | GPIO |
| 58 | I/O | PB1 | |
| 59 | I/O | PB2 | |
| 60 | I/O | PB3 | |
| 61 | I/O | PB4 | |
| 62 | I/O | EXTPWR | |
| 63 | I/O | PA7 | GPIO |
| 64 | I/O | PA6 | |
| 65 | I/O | PA5 | |
| 66 | I/O | PA4 | |
| 67 | I/O | PA3 | |
| 68 | I/O | PA2 | |
| 69 | I/O | PA1 | |
| 70 | I/O | PA0 | |
| 71 | O | PNPC | PnP I2C bus clock |
| 72 | I/O | PNPD | PnP I2C bus data |