SIMM-Sys CPU card scSharc

Preliminary

Description

The scSharc cards from the SIMM-Sys CPU card line are built around the Analog Devices ADSP-21065L 32-bit floating-point DSP processor.

The processor is running on 66MHz and performing up to 3 operations over one clock. Its 68kBytes of integrated dual-ported zero-wait-state RAM adds to the top performance. It also features a unified 8-ported register file, 16 address generators and a high performance DMA engine. The DSP core is surrounded with an impressing number of peripherials. There are two high-speed serial ports, general-purpose I/O, host interface (not used on the SIMM-Sys CPU card) and a high performance memory interface with built-in SD-RAM support.

The card completes this set of excellent features with up to 8MBytes of 16-bit FLASH memory and up-to 64MBytes of 32-bit SDRAM memory.

This CPU card is designed to perform demanding DSP tasks such as high-speed data acquisition or image processing with maximum precision.

For more budget-minded customers there is a scaled-down version of the controller. The only difference between the full-blown and the lc (Low-Cost) version is the amount of SDRAM and FLASH memory it contains.

Software can be developed for this card using the VisualDSP++ software available from Analog Devices. I know about no free development tool-chain for this DSP processor. However a demo version can be obtained from Analog Devices.

Specification

The card is available in several configurations. Some typical ones are shown here as examples

scSharc scSharc-lc

Clock speed 33 33 MHz

CPU speed 66 66 MHz

SRAM memory 68 68 kByte

SDRAM memory 64 8 MByte

FLASH memory 8192 512 kByte

Power supply 3.3 3.3 V

	scSharc	scSharc-lc
Clock speed	33	33	MHz
CPU speed	66	66	MHz
SRAM memory	68	68	kByte
SDRAM memory	64	8	MByte
FLASH memory	8192	512	kByte
Power supply	3.3	3.3	V

SIMM-Sys bus pin-out

Pin No.	Dir	Name	Description
1	O	RD	Active low read select signal.
2	O	UWE	Active low write select signal. Upper byte.
3	O	LWE	Active low write select signal. Lower byte.
4	I	RESET	Active low reset signal.
5	O	SEL0	Active low peripherial select signal.
6	O	SEL1	Active low peripherial select signal.
7	O	SEL2	Active low peripherial select signal.
8	I	IRQ0	Active low interrupt signal. Can be edge or level sensitive.
9	I	IRQ1	Active low interrupt signal. Can be edge or level sensitive.
10	I	IRQ2	Active low interrupt signal. Can be edge or level sensitive.
11	O	A0	Address lines
12	O	A1
13	O	A2
14	O	A3
15	O	A4
16	O	A5
17	O	A6
18	O	A7
19	O	A8
20	O	A9
21	I/O	D0	Data lines
22	I/O	D1
23	I/O	D2
24	I/O	D3
25	I/O	D4
26	I/O	D5
27	I/O	D6
28	I/O	D7
29	I/O	D8
30	I/O	D9
31	I/O	D10
32	I/O	D11
33	I/O	D12
34	I/O	D13
35	I/O	D14
36	I/O	D15
key
37	PWR	WAIT	Active low signal to introduce wait-states in the access cycles. Must be driven. with an open-collector driver. The pull-up resistor is provided on the CPU card.
38	PWR	GND	Ground
39	PWR	GND	Ground
40	PWR	VCC_3	3.3V nominal power supply.
41	PWR	VCC_3	3.3V nominal power supply.
42	PWR	VCC_2_5	2.5V nominal power for core supply. (not used on this card)
43	PWR	VCC_1_8	1.8V nominal power for core supply. (not used on this card)
44	I	PROG	Active low programming signal.
45	I/O	RCLK0	Read bit-clock for serial port 0
46	I/O	RFS0	Read frame sync for serial port 0
47	I	RD0	Read data for serial port 0
48	I/O	TCLK0	Transmit bit-clock for serial port 0
49	I/O	TFS0	Transmit frame sync for serial port 0
50	O	TD0	Transmit data for serial port 1
51	I/O	RCLK1	Read bit-clock for serial port 1
52	I/O	RFS1	Read frame sync for serial port 1
53	I	RD1	Read data for serial port 1
54	I/O	TCLK1	Transmit bit-clock for serial port 1
55	I/O	TFS1	Transmit frame sync for serial port 1
56	O	TD1	Transmit data for serial port 1
57	I/O	FLAG9	GPIO
58		N.C.
59	O	PWM0	PWM output 0
60		N.C.
61		N.C.
62	O	PWM1	PWM output 0
63	I/O	FLAG0	GPIO
64	I/O	FLAG1
65	I/O	FLAG2
66	I/O	FLAG3
67	I/O	FLAG4
68	I/O	FLAG5
69	I/O	FLAG6
70	I/O	FLAG7
71	O	PNPC	PnP I2C bus clock
72	I/O	PNPD	PnP I2C bus data