Each CPU card should be capable of driving all three SELx pins and receive interrupts on all three IRQx pins. Each extension card should be hard-wired to response to SEL0 and send IRQ requests on IRQ0 line. It is the responsibility of the motherboard to route the appropriate SELx and IRQx signals to the appropriate pins of the CPU card socket.
It is also the responsibility of the motherboard to connect (upon request) the PnP EEPROM found on the extension cards and the motherboard to the CPU PnP pins. As the CPU cannot address more the one EEPROM at a time this connection must be made through special I2C multiplexer ICs. Currently the PCA9544 four-port multiplexer is supported from Philips. If the motherboard does not contain any extension sockets the multiplexer can be omitted and the PnP EEPROM can be hardwired to the CPU socket pins. If a multiplexer is used, it's port 0 should be connected to the extension socket which is addressed by SEL0. Port1 should be connected to extension socket addressed by SEL1 and so on. Thus once the CPU card have read the PnP information it knows how to access that peripherial.
Most motherboards will provide peripherial functions for the CPU card. From the CPU card's viewpoint the motherboard peripherials should appear as a normal extension card. It is recommended to use SEL0 and IRQ0 communicating with motherboard peripherials.
Motherboards are also required to provide sufficient power supply for the CPU and optional extension cards. The maximal power requirement of the SIMM-Sys cards in general are not specified, so this might cause incompatibility problems. The designer of the motherboard should count on the power requirements of the selected CPU and extension cards. The 3.3V power supply is mondatory. Other suppies (2.5V and 1.8V) are optional. However if those supplies are not provided some CPU and extension cards will not work. As a rule of thumb one can assume that none of the cards will consume more than 500mA on a power-line and will not use both core-power lines. Most of the cards will require much less power!
The motherboard's responsibility is to provide proper power-on initialization for the SIMM-Sys cards. The RESET line should be held low for at least 50ms after power-up. This will allow the optional CPU PLLs to stabilize. The RESET signal should be a clear LVCMOS signal. A hysteresis might or might not provided on the RESET input of the card. Some cards might not come-up immediately after pulling RESET pin up. The motherboard should not assume operation started immediately after pulling RESET to high. CPU cards are required to drive at least valid SELx signals (logic high or HiZ) under all conditions. Thus Motherboards should provide proper pull-up on SELx lines.
As the whole SIMM-Sys system, bus operation and timing is also loosely defined. The principle of the operation will be the same in all cases however the exact timing might vary from CPU card to CPU card.
The most important timing parameter is cycle length. This parameter can be defined by the extension card (through it's PnP configuration data). The CPU card is required to access the card within the limits of the specification. Some cards can access different extension cards with different speed (number of wait-states) some can not. External wait-state insertion (using the WAIT pin) might or might not be supported by the CPU card so it's use is not recommended.
Transactions are denoted by the rising edge of the SELx signals. It is guarantied that Addr, Data, RD, xWE signals are stable on the rising edge of the SELx signals. Setup times can be specified by the extension card however it is not guarantied that the all signals are stable on the falling edge of the SELx signal. Read operation is denoted by the RD signal being low. Byte and Word reads are not distinguished on the bus. It's the responsibility of the CPU card to multiplex correct byte down to the lower 8-bits of it's internal data-bus when odd bytes are read. Addresses on the SIMM-Sys bus are always 16-bit word addresses. Write operations are denoted by the proper xWR signals being low. For odd byte writes data is presented on Data(15..8) for even data writes data is presented on Data(7..0) signals. However for all write operations all Data-lines might be driven to active state. Word writes are denoted by both xWR signals being low. Some CPU cards are not capable of handling 8-bit data. Those cards will always issue Word write cycles. So it's not recommended to develop extension cards or motherboards relying on odd-byte only write cycles. 8-bit peripherials should use LWR as their write signal and map their addresses to even bytes. (In practice it means that 8-bit peripherials should use Addr(9..0) as their address bus, Data(7..0) as their data-bus and RD and LWR as their RD and WR signals.) For such peripherials it's not required to driver DATA(15..8) to valid level upon read operations.
The motherboard might or might not provide pull-up resistors on DATA-lines. It is recommended however to do so as it might save power.
CPU cards are not required to provide pull-ups on ADDR or DATA lines.
Some CPU cards might issue burst-like read or write requests. In burst-line reads SELx and RD lines remain low while ADDR lines goes to another value. They require the peripherial to present the new value on the DATA lines after a specified (programmable) time. In burst-like writes the xWR lines toggle while SELx remains low. A new DATA and ADDR is presented and the peripherial is required to perform the new WR operation. The support for such burst-like operation form the peripherials is optional but must be stated correctly in the configuration EEPROM.
Peripherials might need a minimum inactive time between bus transactions. This time can be specified also in the PnP configuration. However this time should be the same for all addresses used by the peripherial and be the same throughout the whole operation of the device. If it is not the case, special handling routines might be utilized or IRQ driven operation is implemented.
The SIMM-Sys bus is a single-master bus. No other bus-master than the single CPU card can present on the bus and no DMA operation is supported. If such operation is required it can be implemented using some of the user-defined pins on the SIMM-Sys bus however this will present sever compatibility problems.